VHDL

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comp.lang.vhdl
Y
string declaration
  • Yann Sarrazin
Replies
4
Views
35K
Thomas B.
T
M
AWGN in VHDL
  • MACEI'S
Replies
5
Views
5K
ndrabik
N
M
decoder
  • Max
Replies
2
Views
2K
Egbert Molenkamp
E
K
Manipulating with the T1, T0 and TX in a SAIF file.
  • Kelvin Tsai @ Singapore
Replies
0
Views
1K
Kelvin Tsai @ Singapore
K
K
Synthesizing a design with RAM.
  • Kelvin @ Singapore
Replies
0
Views
1K
Kelvin @ Singapore
K
W
Are all the signals read in the process should appear in the sensitivity list of the process?
  • walala
Replies
3
Views
2K
Allan Herriman
A
C
Design Flow: STA to Synthesis
  • Crimson_M
Replies
1
Views
2K
Brian Drummond
B
K
Timing Diagram to HDL Translation
  • Kieran Francisco
Replies
9
Views
2K
VhdlCohen
V
W
any VHDL books on low resource(throughput, area, power trade-off) design?
  • walala
Replies
0
Views
1K
walala
W
W
SOS! newbie question about synthesizable VHDL : synthesis run successfully but post-synthesis failed
  • walala
Replies
4
Views
2K
Technology Consultant
T
V
predefined function/library
  • Vincent
Replies
3
Views
2K
Egbert Molenkamp
E
W
what are the possible reasons that successful pre-synthesis simulation + successful synthesis = fail
  • walala
Replies
4
Views
3K
Ralf Hildebrandt
R
S
ModelSim and the Xilinix web pack unisim libraries
  • Stephen Lohning
Replies
1
Views
2K
Barry Brown
B
J
Question: inout signal assignment
  • John Potter
Replies
1
Views
3K
Renaud Pacalet
R
W
is function conv_std_logic_vector() synthesizable?
  • walala
Replies
2
Views
9K
Ralf Hildebrandt
R
S
switching problem
  • Simone Winkler
Replies
5
Views
1K
William Wallace
W
W
How to get a slice of INTEGER type out?
  • walala
Replies
1
Views
3K
MM
M
M
array of component
  • Max
Replies
1
Views
946
Ralf Hildebrandt
R
M
warning?
  • Max
Replies
2
Views
3K
eadgbe
E
M
(newbie) 2 read/write register
  • Max
Replies
1
Views
5K
eadgbe
E
W
newbie question about <= and :=? what's the difference?
  • walala
Replies
3
Views
2K
Egbert Molenkamp
E
S
function read_eeprom(addr); possible?
  • steve
Replies
3
Views
2K
Mike Treseler
M
M
(newbie) processo or not process?
  • Max
Replies
7
Views
960
J. Bhasker
J
M
newbie question about decoder
  • Max
Replies
0
Views
1K
Max
M
W
Prioritising nets
  • Willem Oosthuizen
Replies
3
Views
1K
Renaud Pacalet
R
M
newbie question about type declaration
  • Max
Replies
2
Views
850
Colin Marquardt
C
R
Simple combinatorial logic consuming major resources?
  • RZ
Replies
2
Views
1K
RZ
R
W
Coding style to prioritize certain inputs
  • Willem Oosthuizen
Replies
5
Views
1K
Mike Treseler
M
M
another newbie question about vhdl
  • Max
Replies
2
Views
919
Ralf Hildebrandt
R
M
Complex digital ICs visual simulation?
  • Michael
Replies
0
Views
1K
Michael
M
M
Different types of ASICs?
  • Michael
Replies
1
Views
2K
David Jones
D
K
What does + synthesize to?
  • Kload
Replies
1
Views
985
Ralf Hildebrandt
R
S
generate testbench for array signals
  • Simone Winkler
Replies
1
Views
1K
Pedro Claro
P
P
Configuration of multiple architectures
  • Panic
Replies
1
Views
3K
Egbert Molenkamp
E
V
VHDL design and ModelSim
  • Vilvox
Replies
2
Views
1K
Vilvox
V
C
A student's question
  • Chen Bin
Replies
7
Views
1K
Kot
K
K
Using "others" in if statement
  • Kot
Replies
11
Views
1K
Renaud Pacalet
R
W
where can I find book/resources talking about DSP design using VHDL?
  • walala
Replies
1
Views
1K
Jonathan Bromley
J
W
how to design this datapath unit for DSP using VHDL/Verilog?
  • walala
Replies
3
Views
7K
walala
W
M
Inverted Clock in ACEX1K
  • Manfred Balik
Replies
1
Views
2K
Marc Guardiani
M
M
(newbie) writing a state machine
  • Max
Replies
3
Views
1K
Max
M
W
how to read and understand long written VHDL code?
  • walala
Replies
6
Views
4K
Marcus Harnisch
M
S
USB Controller
  • SneakerNet
Replies
0
Views
1K
SneakerNet
S
J
create 400 clocks delay for a signal
  • john
Replies
1
Views
1K
Kai Harrekilde-Petersen
K
S
Address muxing from multiple sources
  • Salman Sheikh
Replies
0
Views
1K
Salman Sheikh
S
S
assigning output to input
  • Simone Winkler
Replies
1
Views
5K
Jonathan Bromley
J
J
others in state machine
  • Jerker Hammarberg \(DST\)
Replies
3
Views
5K
Mike Treseler
M
K
Is it a bug of synplify?
  • Kot
Replies
3
Views
1K
Kot
K
S
Please help me!!! ModelSim question
  • Simone Winkler
Replies
1
Views
1K
Mike Treseler
M
P
Need help on how to use functions correctly
  • Panic
Replies
0
Views
998
Panic
P

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