VHDL

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comp.lang.vhdl
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Convert ADC output format to DAC input
  • snake368
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7
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1K
Andy
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need vhdl code for 8 bit simple cpu
  • say
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0
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1K
say
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VHDL code PROBLEM ,how to create shift left operation withoutregister in vhdl
  • Wing Chun
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7
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3K
Andy
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Hexadecimal value (literal) as function parameter, is it possible?
  • wimille
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3
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1K
Andy
A
A
configurable number of interfaces
  • ananth kamath
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5
Views
858
ananth kamath
A
A
Definition Multiply and Division in VHDL
  • Adnan86
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0
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2K
Adnan86
A
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mutliple input through same input lines
  • paviinelec
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0
Views
831
paviinelec
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Which function takes precedence when multiple are visible?
  • kevin.neilson
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1
Views
841
KJ
K
B
Architecture name through hierarchy
  • blaise.mulliez
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6
Views
995
KJ
K
G
image compression using golomb-rice algorithm
  • gokuldeep
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0
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2K
gokuldeep
G
E
precedence of a downto clause
  • ejubenville
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0
Views
865
ejubenville
E
A
Digital Counter Error
  • alextc1
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0
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1K
alextc1
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"Non-static aggregate with multiple choices has non-static otherschoice."
  • rickman
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5
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1K
rickman
R
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Feedback loop in VHDL-AMS
  • gdlicciardo
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0
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1K
gdlicciardo
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C
Clock Switching in VHDL/ Actel igloo nano device
  • cory.shol
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9
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2K
Dave Higton
D
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Conditional Assignments in Constants
  • kevin.neilson
Replies
4
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3K
kevin.neilson
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Mathematical formula implementation
  • vhdl_newbie
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15
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1K
vhdl_newbie
V
N
System Verilog
  • nivparsons
Replies
1
Views
932
HT-Lab
H
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Memory Mapped Register Help
  • KAY
Replies
4
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2K
KAY
K
S
Data type conversion
  • Stachu Chebel
Replies
1
Views
814
KJ
K
L
VHDL code verification
  • Lukáš Král
Replies
8
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1K
Allan Herriman
A
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AMBA AHB COMPLAINT MEMORY CONTROLLER
  • VINZ4754
Replies
0
Views
887
VINZ4754
V
G
Resolved vs. Unresolved standard logic, and when to get away with using each
  • gsteemso
Replies
8
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2K
Andy
A
K
Hardware Acceleration VGA graphics controller
  • KAY
Replies
6
Views
1K
maleklamari
M
F
Is this kind of writing useful?
  • fl
Replies
2
Views
910
Andy
A
M
Immunizing Design/Simulation From Unknowns
  • M. Norton
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3
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1K
GaborSzakacs
G
A
Set std_logic_vector values in a range
  • anasimtiaz
Replies
5
Views
993
Andy
A
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ethernet on spartan 3an
  • revkarol
Replies
5
Views
2K
bknpk
B
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What is the difference of "array (63 downto 0) of ...." and "array (0to 63) of ...."
  • fl
Replies
5
Views
1K
Andy
A
S
VHDL-AMS: Simulating a closed model in Mentor Graphics System Vision
  • shai.lesh
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0
Views
2K
shai.lesh
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F
Why does Modelsim not display some signals?
  • fl
Replies
2
Views
998
HT-Lab
H
I
Assign a value to a position in a std_logic_vector
  • ionutcazacu2007
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10
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2K
Thomas Stanka
T
F
Does the last elseif run or not?
  • fl
Replies
6
Views
1K
HT-Lab
H
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Free PDF Combinational Logic book download that introduces Quartus II
  • prairiefalcons
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1
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1K
padthaiken
P
N
to_unsigned as an expression in an aggregate
  • Nick Bayard
Replies
6
Views
1K
nbayard
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Why ever use std_logic_vector intead of signed/unsigned?
  • kevin.neilson
Replies
11
Views
2K
KJ
K
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For verification, what's the best way to introduce delay offsetbetween a DUT's data array?
  • py
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1
Views
996
goouse99
G
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compilation errors with no clues(modelsim)
  • Emmanuel
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2
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1K
Emmanuel
E
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Scott Cooper's book on VHDL-AMS
  • shai.lesh
Replies
0
Views
854
shai.lesh
S
A
concurrent assertion statement and delta races
  • Allan Herriman
Replies
16
Views
2K
Allan Herriman
A
B
Emacs VHDL-mode Next-Error, Previous-Error, and First-Error are not working...?
  • BlackHelicopter
Replies
2
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2K
BlackHelicopter
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VHDL-2008 Reference Book
  • rickman
Replies
6
Views
970
rickman
R
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Vhdl syntax for generate ...
  • olivier90dir
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7
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2K
rickman
R
B
Emacs, VHDL Mode - Upper Case Enum Values & Upper Case Constants (not working)?
  • BlackHelicopter
Replies
0
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2K
BlackHelicopter
B
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Sometimes I Just Don't Get the Tools
  • rickman
Replies
6
Views
816
rickman
R
V
What is a signal?
  • valtih1978
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1
Views
703
rickman
R
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Error (10028): Can't resolve multiple constant drivers for net"light" at LED.vhd(25) NEED HELP!
  • willmann817
Replies
5
Views
2K
Andy
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the most beautiful\valuable vhdl-projects (categorized)
  • troll greenЪ
Replies
0
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1K
troll greenЪ
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noob question on loops
  • Karol Hennessy
Replies
16
Views
1K
rickman
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V
assignment constraint check time
  • Valentin Tihhomirov
Replies
4
Views
630
valtih1978
V

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