VHDL

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comp.lang.vhdl
R
I need an or_reduce for an array of std_logic_vectors
  • Richard Nicholas
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11
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1K
alb
A
K
Verilog Binary Divider
  • Kristo Godari
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2
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6K
Nikolaos Kavvadias
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DIVIDE-BY-TWELVE DECODE COUNTERS( SN7492)
  • saeed omer
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3
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1K
Rob Gaddi
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Lattice EFB I2C core works in simulation, but not on hardware
  • littlegamer
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3
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5K
lars555
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VHDL sharing components?
  • Matt Johnson
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1
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965
GaborSzakacs
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Partnership Request
  • Dan Wawa
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2
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790
GaborSzakacs
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timing verification
  • alb
2
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22
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2K
Mike Treseler
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FIR Filter Transposed Form VHDL
  • Ste_ee
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12
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2K
Ste_ee
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How to design 4 bit 4:1 multiplexer
  • Faisal Kabir
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1
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1K
Jim Lewis
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fifo reading
  • revkarol
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3
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1K
revkarol
R
A
combinational loops
  • alb
2 3
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54
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4K
alb
A
V
How did Ashenden know about STD_INPUT?
  • valtih1978
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7
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1K
Andy
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B
ModelSim 'vmake' and bash is not generating properly formatted Makefile
  • BlackHelicopter
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0
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2K
BlackHelicopter
B
A
bit slice in vectors
  • alb
Replies
4
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1K
Andy
A
A
vhdl & verilog simulation
  • alb
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4
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1K
pini
P
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autonomous monitors
  • alb
Replies
2
Views
991
alb
A
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return the (value of) assignment
  • valtih1978
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2
Views
960
Tim McBrayer
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data type choice
  • alb
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7
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943
KJ
K
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Reflexions about a new HDL language
  • Mister_J
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1
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1K
simguru
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parametric vector slices
  • alb
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1
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664
Andy
A
A
concurrent signal assignment in a process
  • alb
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3
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1K
Andy
A
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Active sources
  • valtih1978
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10
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1K
valtih1978
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addition not work in vhdl
  • marcin00022
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6
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1K
pini
P
G
Equations in Vector Range Definitions
  • guyanalog
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2
Views
790
Andy
A
R
Possible Quartus Bug
  • Rob Gaddi
Replies
4
Views
2K
Tricky
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abstracting the client/server protocol
  • alb
Replies
5
Views
900
Andy
A
A
Fixed Point + Math Package/Library Verilog/VHDL
  • abdkahnz
Replies
1
Views
2K
goouse99
G
S
confusion about delta time
  • sensor
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4
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1K
Paul Uiterlinden
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verify the IP filter using vhdl linked lists
  • bknpk
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1
Views
935
pini
P
C
How to give one clock cycle in VHDL testbench?
  • Chris Waugh
Replies
5
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1K
goouse99
G
B
AHB/APB graduate project
  • bknpk
Replies
0
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1K
bknpk
B
B
Is a block spoof IP filter in hardware (VHDL design) is required
  • bknpk
Replies
0
Views
877
bknpk
B
C
Any one who can help me out to implement 3 short algorithms in VHDL?I am ready to pay
  • Chris Waugh
Replies
0
Views
834
Chris Waugh
C
A
ModelSim ** Warning: <foo.vhd> Choice in CASE statement alternativemust be locally static.
  • alb
Replies
5
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2K
Andy
A
A
[cross-post] vlib, vmap, vcom, how it all works...
  • alb
Replies
0
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2K
alb
A
A
vmk and simulation
  • alb
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3
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1K
Bart Fox
B
A
managing vhdl projects with Makefiles
  • alb
Replies
7
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2K
alb
A
H
Change record elements
  • hssig
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3
Views
763
hssig
H
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problem mixing vhdl and verilog using tristate
  • teroer
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1
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1K
teroer
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Can anyone help me out to implement some VHDL codes for some cash.
  • chris.waugh190490
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3
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1K
chris.waugh190490
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OS-VVM crosscoverage vs directed testing
  • alb
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8
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1K
alb
A
A
*URGENT* Anyone keen to helpout to design a Elevator controller VHDLfile using altera *URGENT*
  • asuraseed
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1
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1K
alb
A
A
elevator controller
  • asuraseed
Replies
2
Views
844
Paul Uiterlinden
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Want to understand the logic of a code
  • lkp
Replies
0
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773
lkp
L
C
Conditional Compile Generate statements
  • Cory Shol
Replies
5
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2K
Andy
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if statement problem
  • lokesh kumar
Replies
13
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1K
Paul Uiterlinden
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Squaring of a binary number
  • lokesh kumar
2
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24
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2K
lokesh kumar
L
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Simulating a bidirectional bus delay
  • Fredxx
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4
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1K
Fredxx
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Doubts on processes using a single clock.
  • mindentropy
Replies
4
Views
949
Andy
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Can anyone help me to design a n bit input and n bit output shift register
  • lokesh kumar
Replies
1
Views
1K
goouse99
G

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