VHDL

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comp.lang.vhdl
F
Questions about negate a negative number
  • fl
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1
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1K
GaborSzakacs
G
F
Can wild letters be used in case statements?
  • fl
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8
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1K
HT-Lab
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F
Why does this if process wrong?
  • fl
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5
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898
Nicolas Matringe
N
J
problem with unsigned vs std_logic_vector
  • jlodman
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11
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2K
Andy
A
C
VHDL verification using Python via VHPI
  • Chris Higgs
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0
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2K
Chris Higgs
C
J
getting the range from a member of a record.
  • jlodman
Replies
5
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2K
Andy
A
R
Execution of a process without an event occurring in its sensitivity list
  • Raja Harsha
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4
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1K
Daniel Kho
D
L
loop 10000 iterations limit in quartusII.
  • Luis Cupido
Replies
6
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1K
Daniel Kho
D
N
Multi-function, universal, CORDIC IP available from the OpenCores website
  • Nikolaos Kavvadias
Replies
0
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1K
Nikolaos Kavvadias
N
E
Need help designing a circuit in Verilog
  • eithriad
Replies
2
Views
724
Nikolaos Kavvadias
N
N
VHDL simulator supporting SCE-MI or vendor's DPI?
  • Nikolaos Kavvadias
Replies
1
Views
967
HT-Lab
H
A
[cross-post]path verification
  • alb
2
Replies
31
Views
2K
HT-Lab
H
B
Integers which are more than 32 bit
  • bipper
Replies
1
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1K
Paul Uiterlinden
P
O
precompilation 'Vhdl' syntax
  • olivier90dir
Replies
1
Views
780
Olivier Dir
O
A
Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
  • alb
Replies
7
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2K
Andy
A
A
[cross-post][long] svn workflow for fpga development
  • alb
Replies
7
Views
995
alb
A
O
How dofor using generate or loop for this process ?
  • Olivier Dir
Replies
3
Views
960
Daniel Kho
D
R
sensitivity list
  • rkdkkr
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0
Views
685
rkdkkr
R
R
22v10
  • rkdkkr
Replies
0
Views
918
rkdkkr
R
Y
how to avoidind multisourcing on signal
  • yogesh malekar
Replies
5
Views
903
Daniel Kho
D
S
verilog questions
  • sandhya pochiraju
Replies
1
Views
1K
rickman
R
Y
VHDL code error
  • Youssef Ahmed
Replies
10
Views
1K
Andy
A
T
Design toplevel module as schematic?
  • Tobias Baumann
2
Replies
22
Views
3K
Anssi Saari
A
G
VHDL Synchronizer Function
  • genogiapasetti
Replies
2
Views
2K
Dio Gratia
D
S
conv N/A _ with_Virtex5
  • Salah Kortli
Replies
0
Views
741
Salah Kortli
S
V
Separate elaboration and parsing
  • valtih1978
Replies
6
Views
958
valtih1978
V
S
code question
  • sk3ptic
Replies
2
Views
984
sk3ptic
S
B
SPI; simulating an input (rx)
  • Brandon Spiteri
Replies
8
Views
1K
KJ
K
A
FFT CALCULATION USING DISTRIBUTIVE ALGORITHM.
  • ajit yadav
Replies
2
Views
883
KJ
K
A
erreur VHDL
  • Ayoub
Replies
3
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2K
Sean Durkin
S
A
erreur VHDL 2
  • Ayoub
Replies
1
Views
775
alb
A
T
Can I replace this procedure with a function (VHDL 2008 problem)?
  • Tricky
Replies
6
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1K
Tricky
T
O
Writing testbench tools. Suggestions?
  • o pere o
Replies
7
Views
1K
Andy
A
M
VHDL to SystemC
  • moogyd
Replies
3
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2K
moogyd
M
A
PC function code
  • Amr Kassab
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0
Views
897
Amr Kassab
A
A
Help code VHDL
  • Ayoub
Replies
2
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1K
Ayoub
A
A
Array VHDL
  • Ayoub
Replies
3
Views
1K
Tricky
T
A
demande plz
  • Ayoub
Replies
3
Views
827
Nikolaos Kavvadias
N
A
Array of Modulation BPSK
  • Ayoub
Replies
0
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1K
Ayoub
A
A
code vhdl
  • Ayoub
Replies
1
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2K
Rob Gaddi
R
P
Code owuld compile before, now doesnt recognise '='
  • professor_dikweed
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0
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1K
professor_dikweed
P
C
Parallel load register 4 bit without using instantiation
  • chirag.nitb
Replies
1
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1K
rickman
R
A
Multiplication VHDL
  • Ayoub
Replies
4
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3K
fredrick
F
K
Verilog: Why the "maxcount" cannot keep its max value but changeswith the "count"?
  • kaiyutony
Replies
4
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1K
rickman
R
N
Hash 256 function
  • niv
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0
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883
niv
N
S
VHDL
  • Sohaib
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1
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1K
cmelias
C
E
problem executing testbench. error in coding
  • ezzyrul
Replies
1
Views
2K
cmelias
C
Divyesh Patel
VHDL program error
  • Divyesh Patel
Replies
2
Views
6K
cmelias
C
R
wimax interleaver
  • rkavipriya
Replies
0
Views
1K
rkavipriya
R
M
BPSK COSTAS LOOP DEMODULATOR
  • Minesh Darji
Replies
0
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2K
Minesh Darji
M

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