VHDL

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comp.lang.vhdl
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stepper motor
  • Sweta Dauhawoo
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Sweta Dauhawoo
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VHDL to machine code converter
  • neshatkorivand
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jstr3811
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how to generate a Staircase wave using vhdl code?
  • maheshr
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maheshr
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merge sort
  • divyavani
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divyavani
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I want VHDL code for n x n matrix multiplication without using pipelining
  • pritam
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pritam
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Vhdl code for octal to binary conversion
  • Jaison jacob
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Jaison jacob
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alternative variable length code
  • sowndarya
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sowndarya
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nine code compression
  • sowndarya
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1K
sowndarya
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error in serial right operation in modelsim10.4a
  • maneesha zakka
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maneesha zakka
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Implementation a SVM ( SVPWM) in FPGA with VHDL
  • Colllins Nana
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3K
Colllins Nana
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help me to code vending machince with following specification
  • SHAJITH
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1K
SHAJITH
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vhdl
  • rupakala
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rupakala
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Send data from MATLAB to FPGA through USB
  • jose de arimatea
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jose de arimatea
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  • Poll
Is my port map syntax right???? i am not able to find the proper guidance for the error in any book
  • keerthi_raj
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1K
keerthi_raj
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geting error as unxpected symbol read: ". in array initialization
  • mrunal
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mrunal
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FPGA for Frequency Divider
  • _Jaiko007
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1K
_Jaiko007
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4 bit two flipflop sychronizer
  • Bhakti Dedhia
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1K
Bhakti Dedhia
B
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Shift left register using VHDL shift operator : sll trouble
  • Anviori
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2K
Anviori
A
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Minimum period: No path found
  • kiran77
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kiran77
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Floating point library RC
  • Gonzalo
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1K
Gonzalo
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1:8 demux behavioral and structural modeling
  • Ibra1950
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1
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8K
Ibra1950
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and operator overloading
  • eladsolomon
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1K
eladsolomon
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I need a VHDL code
  • Moh
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Moh
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miroslavasadov
pls help me ; vhdl;
  • miroslavasadov
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2K
miroslavasadov
miroslavasadov
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Issue with simulation time - Modelsim PE Student 10.4
  • Rashnak
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1K
Rashnak
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Input ports in VHDL of type string and Boolean
  • Razn_957
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2K
Razn_957
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How to use ufixed when it involves multiplication a number of times?(VHDL question)
  • Anwesa Roy
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2K
Anwesa Roy
A
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2 flip-flop synchronizer
  • andys86498
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1
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3K
netguy63
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Xilinx ISE, expression not globally static inside generic map
  • Zo Ki
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Zo Ki
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VHDL Subtraction two’s complement
  • Alenx
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Alenx
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Mixer-Unit on Altera DE2-115 Cyclone IV
  • Larinayo
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1K
Larinayo
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lms algorithm code
  • alok das gupta
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1K
alok das gupta
A
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conversion from 8bit to 4 bit in vhdl
  • alok das gupta
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1
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3K
Cor
C
C
Illegal sequential statement (VHDL)
  • chiraz
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2K
chiraz
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verilog hdl
  • shachi
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1K
shachi
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Query related to division of 1.122 in mentioned code.
  • Kritika Bhardwaj
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Kritika Bhardwaj
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Comparing Inputs to Outputs Simon Game
  • KC1
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KC1
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need to count constants names in vhdl
  • Ana
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Ana
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Reading an xml file in vhdl
  • sandeepthi
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2K
sandeepthi
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verilog, rtl, simulation
  • akshata@94
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akshata@94
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How to write if statement written in matlab with vhdl ?
  • afef
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afef
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LFSR doesn't generate random values during simulation
  • learni
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1
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1K
Cor
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Cannot Read Data in 1-Port RAM IP Core
  • learni
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learni
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Problem With Mealy Sequence Detector
  • Armand
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1
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1K
Cor
C
C
How to get signal name as a string in a procedure?
  • Cor
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0
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1K
Cor
C
J
Sine wave 200khz , having a digital 16 bit value using VHDL
  • JaneJune
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JaneJune
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reading binary file using vhdl
  • assaad EL Makhloufi
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assaad EL Makhloufi
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sum of a array's element
  • alireza95
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1K
alireza95
A
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Cannot find <math_utility_pkg> in library <ieee_proposed>
  • ADHUL
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1K
ADHUL
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2 JK Circuit in VHDL
  • dumdumdum
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1K
dumdumdum
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